Atrenta will discuss what RTL signoff requirements are needed for SoC designers in China, South Korea and Taiwan at their upcoming seminars in September and October. Click here for more information.
We often think that we’ve got the timing job nailed down and that there aren’t any problems that we can’t easily, almost routinely solve. Using timing exceptions to optimize synthesis or P&R shouldn’t be a problem. However, making an error when specifying timing exceptions can possibly shut down a design project. Take a look at […]
Before the summer ends and the summer blockbuster movies and DAC become a distant memory (still shaking my head over The Lone Ranger’s flop), let me just share Mike Gianfagna’s vision for next summer’s blockbuster. It’s a tad more like Terminator 2 than the masked man and Tonto. And it may not be too far […]