Back in December, Liz and I figured that it’d be a good time to ask chip and EDA/IP industry folks: 1) what will chip companies need from their EDA/IP vendors in 2014 and 2) what will we see develop in EDA/IP in 2014? We thought that Jim Hogan could probably respond to both questions. He […]
SKTA Innopartners director Angel Orrantia spoke with the San Jose Mercury’s Peter Delevett on why Silicon Valley’s VC community has to start investing again in hardware. Sure, as Orrantia infers, hardware is tougher (and will probably take longer) to get an exit out of. But hardware is how electronics ultimately works with its human users. So funding […]accelerators, Angel Orrantia, Elevator Pitch, hardware, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?fref=ts, incubators, Lee Public Relations, Peter Delevett, San Jose Mercury News, Semiconductor IP, semiconductors, Silicon, Silicon Beat, silicon valley, SJ Merc, SK telecom Americas, SKTA Innopartners, startups, VC, venture capitol
My colleague Liz Massingill spoke with IPextreme CEO Warren Savage about her approach to PR, i.e., what she wants to accomplish on behalf of her clients. The main message? It’s all about the story…the company’s story…and how Liz creates it, substantiates it, reinforces it. In the end, it’s all about putting a human face on the faceless company to […]creating the PR story for clients, EDA, high tech PR, IPextreme, Lee PR, Liz Massingill, semiconductors, semiIP, Warren Savage
There’s an EDA industry reunion at the Computer History Museum on October 16th. “EDA: Back to the Future” is being put on by EDAC along with several sponsors, and it looks like it will be a night to remember. To learn more about the event and purchase tickets click here. Part of this event is a […]Atrenta, Chip Design, EDA, EDA Consortium, EDAC, Lee PR, semiconductors, SoC, System on Chip
Atrenta will discuss what RTL signoff requirements are needed for SoC designers in China, South Korea and Taiwan at their upcoming seminars in September and October. Click here for more information.
We often think that we’ve got the timing job nailed down and that there aren’t any problems that we can’t easily, almost routinely solve. Using timing exceptions to optimize synthesis or P&R shouldn’t be a problem. However, making an error when specifying timing exceptions can possibly shut down a design project. Take a look at […]